COMPUTER ORGANIZATION AND ARCHITECTURE

Consider a microprogrammed control unit in which the next microinstruction address can be obtained from the current address, an external condition, or an instruction opcode. This mechanism is primarily associated with:

1. Data path design
2. Address sequencing
3. Cache mapping
4. Instruction pipelining

Which of the following best describes the role of microprogramming?

1. It specifies the sequence of control signals needed to execute instructions
2. It increases cache capacity
3. It converts physical addresses into logical addresses
4. It schedules I/O interrupts

Which statement correctly distinguishes segmentation from paging?

1. Paging uses variable-sized blocks, whereas segmentation uses fixed-sized blocks
2. Both always use fixed-sized blocks
3. Paging uses fixed-sized pages, whereas segmentation uses logically defined segments
4. Neither requires address translation

The main disadvantage of programmed I/O compared with DMA is

1. It requires no CPU involvement
2. It requires virtual memory
3. It cannot transfer data
4. It increases CPU involvement during data transfer

During DMA, which sequence most accurately represents the major data-transfer path?

1. I/O device → CPU → memory
2. Memory → CPU → I/O device
3. I/O device ↔ memory, with DMA controller coordinating the transfer
4. CPU ↔ cache only

Which of the following is an example of instruction-level parallelism within a uniprocessor?

1. Executing independent instructions concurrently
2. Connecting multiple computers through a network
3. Increasing disk capacity
4. Increasing memory address width

Which of the following best characterizes a CISC architecture compared with a typical RISC architecture?

1. Simplified instruction set
2. More complex and varied instructions
3. No memory operands
4. Uniform instruction formats only

A 4-stage pipeline has a clock cycle time of 10 ns. Ignoring pipeline fill and drain effects, the approximate throughput after the pipeline is full is

1. 5 ns per instruction
2. 4 ns per instruction
3. 10 ns per instruction
4. 40 ns per instruction

A pipeline has 5 stages, and each stage requires one clock cycle. Ignoring stalls, the number of cycles required to execute 20 instructions is

1. 20
2. 24
3. 25
4. 100

A vector processor operates on vectors containing 64 elements. If one vector instruction performs the same arithmetic operation on all 64 elements, the main advantage is

1. Reduced need for repeated instruction specification
2. Elimination of registers
3. Elimination of all memory accesses
4. Elimination of the control unit

Describe the basic organization of a computer system with a neat block diagram and explain the functions of its major units.

Explain the concept of instruction sets and discuss the major components of an instruction.

Describe the memory hierarchy of a computer system with a suitable diagram and explain the role of each level.

Describe the organization and operation of set-associative memory. Also discuss its advantages and disadvantages.

What is Virtual memory? Describe how it is implemented in a computer system.

Differentiate between paging and segmentation. Illustrate how logical addresses are translated into physical addresses in both schemes.

Provide a detailed comparison among Programmed I/O, Interrupt-Driven I/O and Direct Memory Access in terms of hardware complexity, CPU involvement and data transfer rates.

Compare serial and parallel data communication. Explain why modern computer architectures favour serial over parallel interfaces, considering data skew and hardware cost.

Explain RISC and CISC architectures and compare their major characteristics.

Compare SIMD and MIMD architectures under Flynn's classification. Draw their structural block diagrams and provide real-world examples for each.

Explain the working principle of instruction pipelining using a 4-segment instruction execution model. Illustrate the execution of consecutive tasks using a space-time diagram.

Describe the control and data paths in a pipelined processor with a suitable diagram.

Explain the principals involved in designing a pipelined processor.

Describe the difference between scalar processing and vector processing with respect to memory bandwidth and register design.

Microinstruction Execution

DMA

Interrupt Controller

Memory Interleaving