DIGITAL CMOS VLSI DESIGN

For an n-channel enhancement MOSFET, a conducting channel between source and drain is formed when

1. V_GS = 0
2. V_GS < 0
3. V_GS > V_TH
4. V_DS = 0

The primary purpose of photolithography in IC fabrication is

1. Increase transistor current
2. Transfer a geometric pattern onto the wafer
3. Measure transistor resistance
4. Remove all oxide from the wafer

Increasing the interconnect capacitance in a CMOS circuit generally

1. Reduces propagation delay
2. Eliminates static power
3. Increases threshold voltage
4. Increases propagation delay

For a simple lumped RC interconnect, the approximate 50%-transition delay is

1. RC
2. 5RC
3. 69RC
4. 2RC

The major advantage of CMOS logic over conventional NMOS logic is

1. Higher static power consumption
2. Very low static power dissipation
3. Zero transistor count
4. Absence of complementary devices

An edge-triggered flip-flop changes its stored state

1. Only near a specified clock edge
2. Throughout the entire clock LOW period
3. Throughout the entire clock HIGH period
4. Only when both inputs are HIGH

Which parameter is commonly used to represent the transconductance of a MOSFET?

1. g_m
2. r_o
3. C_ox
4. V_th

Layout design rules specify

1. Only transistor threshold voltage
2. Only supply voltage
3. Geometrical constraints between different layout layer
4. Only transistor gain

The dominant parasitic capacitance of a long on-chip interconnect is generally

1. Wire-to-substrate and wire-to-wire capacitance
2. Oxide capacitance only
3. Junction capacitance only
4. Gate capacitance

In an active-HIGH NOR-based SR latch, the condition S=R=1 is

1. Set
2. Reset
3. Hold
4. Invalid/forbidden

Explain the structure and operation of an n-channel enhancement MOSFET with a neat labeled diagram.

An NMOS transistor has: V_TH=1V, k_n=2 mA/V², V_GS=3 V, V_DS = 4V. Determine: (i) The operating region and (ii) The drain current (I_D).

Explain the CMOS n-Well Fabrication Process.

Explain the design of a full-custom CMOS inverter layout.

Explain Switching Characteristics of a CMOS Inverter.

Explain the operation of an NMOS resistive-load inverter with a neat circuit diagram.

Derive the propagation delay of a CMOS inverter using the equivalent RC model.

A CMOS inverter has an effective pull-down resistance of 2 kΩ and drives a load capacitance of 50 fF.
(i) Calculate the propagation delay
(ii) If the maximum permissible delay is 100 ps, determine whether the design satisfies the requirement.
(iii) Calculate the maximum allowable load capacitance for a delay of 100 ps.

Design and explain a CMOS implementation of: Y=AB + CD.

Explain the structure and working of CMOS transmission gates.

Explain the difference between a latch and a flip-flop.

Explain the operation of an edge-triggered D flip-flop.

Explain the current-voltage characteristics of an NMOS transistor.

Explain the important verification techniques used after CMOS layout design.

Effect of transistor sizing on delay

coupling capacitance

Pass transistor

Master slave configuration