Computer Science & Eng. • 3rd SemesterCore / Standard CurriculumChange Track

Computer Science & Eng. — 3rd Semester Syllabus

Computer Science & Engineering

Browse 3rd Semester PYQs

Credits Allocation Table (L-T-P Structure)

Course TitleCodeLTPCredits
Digital Electronics1053013003
Data Structure and Algorithms1053023003
Object Oriented Programming using JAVA1053033003
Discrete Mathematics and Graph Theory1053043104
Operating System1053053003
Universal Human Values1053063003
Indian Knowledge System1053073000
Digital Electronics Lab105301P0021
Data Structure and Algorithms Lab105302P0021
Object Oriented Programming using JAVA Lab105303P0021
Operating System Lab105305P0021
Internship-I105308---2
TOTAL----25

Digital Electronics

105301
Theory Course • 6 Units
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Unit 1.0: Fundamentals of Digital Systems and logic families

  • Digital signals, digital circuits
  • AND, OR, NOT, NAND, NOR and Exclusive-OR operations
  • Boolean algebra, examples of IC gates
  • Number systems: binary, signed binary, octal hexadecimal number
  • Binary arithmetic, one's and two's complements arithmetic
  • Codes, error detecting and correcting codes
  • Characteristics of digital ICs
  • Digital logic families: TTL, Schottky TTL and CMOS logic
  • Interfacing CMOS and TTL, Tri-state logic

Unit 2.0: Combinational Digital Circuits

  • Standard representation for logic functions K-map representation
  • Simplification of logic functions using K-map
  • Minimization of logical functions
  • Don't care conditions
  • Multiplexer, DeMultiplexer/Decoders
  • Adders, Subtractors, BCD arithmetic
  • Carry look ahead adder, serial adder, ALU
  • Elementary ALU design, popular MSI chips
  • Digital comparator, parity checker/generator
  • Code converters, priority encoders
  • Decoders/drivers for display devices
  • Q-M method of function realization

Unit 3.0: Sequential circuits and systems

  • A 1-bit memory, the circuit properties of Bistable latch
  • The clocked SR flip flop
  • J-K-T and D types flip flops
  • Applications of flip flops
  • Shift registers, applications of shift registers
  • Serial to parallel converter, parallel to serial converter
  • Ring counter, sequence generator
  • Ripple (Asynchronous) counters, synchronous counters
  • Counters design using flip flops
  • Special counter IC's, asynchronous sequential counters
  • Applications of counters

Unit 4.0: A/D and D/A Converters

  • Digital to analog converters: weighted resistor/converter
  • R-2R Ladder D/A converter
  • Specifications for D/A converters
  • Examples of D/A converter ICs
  • Sample and hold circuit
  • Analog to digital converters: quantization and encoding
  • Parallel comparator A/D converter
  • Successive approximation A/D converter
  • Counting A/D converter, dual slope A/D converter
  • A/D converter using Voltage to frequency and voltage to time conversion
  • Specifications of A/D converters
  • Example of A/D converter ICs

Unit 5.0: Semiconductor memories

  • Memory organization and operation
  • Expanding memory size
  • Classification and characteristics of memories
  • Sequential memory
  • Read only memory (ROM)
  • Read and write memory (RAM)
  • Content addressable memory (CAM)
  • Charge de coupled device memory (CCD)
  • Commonly used memory chips
  • ROM as a PLD

Unit 6.0: Programmable logic devices

  • Programmable logic array
  • Programmable array logic
  • Complex Programmable logic devices (CPLDS)
  • Field Programmable Gate Array (FPGA)

Data Structure and Algorithms

105302
Theory Course • 6 Units
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Unit 1.0: Introduction

  • Basic Terminologies: Elementary Data Organizations
  • Data Structure Operations: insertion, deletion, traversal etc.
  • Analysis of an Algorithm
  • Asymptotic Notations
  • Time-Space trade off

Unit 2.0: Stacks and Queues

  • ADT Stack and its operations: Algorithms and their complexity analysis
  • Applications of Stacks: Expression Conversion and evaluation
  • Corresponding algorithms and complexity analysis
  • ADT queue, Types of Queue: Simple Queue, Circular Queue, Priority Queue
  • Operations on each Type of Queues: Algorithms and their analysis

Unit 3.0: Linked Lists

  • Singly linked lists: Representation in memory
  • Algorithms of several operations: Traversing, Searching, Insertion, Deletion
  • Linked representation of Stack and Queue
  • Header nodes, doubly linked list: operations and algorithmic analysis
  • Circular Linked Lists: all operations and complexity analysis

Unit 4.0: Searching, Sorting and Hashing

  • Linear Search and Binary Search Techniques and complexity analysis
  • Objective and properties of different sorting algorithms
  • Selection Sort, Bubble Sort, Insertion Sort, Quick Sort, Merge Sort, Heap Sort
  • Performance and Comparison among all methods
  • Hashing

Unit 5.0: Trees

  • Basic Tree Terminologies
  • Different types of Trees: Binary Tree, Threaded Binary Tree, Binary Search Tree, AVL Tree
  • Tree operations and algorithms with complexity analysis
  • Applications of Binary Trees
  • B Tree, B+ Tree: definitions, algorithms and analysis

Unit 6.0: Graph

  • Basic Terminologies and Representations
  • Graph search and traversal algorithms
  • Complexity analysis

Object Oriented Programming using JAVA

105303
Theory Course • 6 Units
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Unit 1.0: OOP Concepts and Java Programming

  • Introduction to Java: History of java, Java buzzwords
  • Basics of Java programming
  • Difference between procedural and object-oriented programming paradigm
  • Need for OOPs paradigm, OOPs features, advantages of oops
  • JDK, JRE and JVM
  • Data types, variables, operators
  • Control structures including selection, looping
  • Java methods
  • Compilation and execution of simple program

Unit 2.0: Objects, Classes, and Constructors in Java

  • Objects and Classes: Basics of objects and classes in java
  • Declaring objects, new keyword
  • Defining and calling methods in class
  • Array of Objects
  • Constructors, Different types of Constructors
  • Overloading Methods and Constructors
  • Method Binding, Overriding and Exceptions
  • Passing Object as parameters, returning object
  • Static members
  • Concept of Access Modifiers (Public, Private, Protected, Default)
  • this Keyword, garbage Collection, finalize() method
  • Nested and Inner Classes
  • Exploring string class

Unit 3.0: Inheritance, Interfaces and Packages

  • Inheritance: Inheritance hierarchies, Benefits of Inheritance
  • Super and subclasses, member access rules, super keyword
  • Preventing inheritance: final classes and methods
  • The object class and its methods
  • Polymorphism: Dynamic binding, method overriding
  • Abstract classes and methods
  • Interface: Interfaces vs Abstract classes
  • Defining an interface, implement interfaces
  • Accessing implementations through interface references, extending interface
  • Packages: Defining, creating and accessing a package
  • Understanding CLASSPATH, importing packages

Unit 4.0: Exception Handling

  • Introduction to error and exception
  • Error vs Exception
  • Concepts of Exception Handling
  • Benefits of exception handling
  • Exception types, exception hierarchy
  • Checked and unchecked exceptions
  • Usage of try, catch, throw, throws and finally
  • Multiple catch clauses, nested try statements
  • Re throwing exceptions
  • Creating own exception sub classes

Unit 5.0: Introduction to Multithreading

  • Differences between multiple processes and multiple threads
  • Thread states
  • Creating threads, interrupting threads
  • Thread priorities
  • Synchronizing threads, inter thread communication

Unit 6.0: Files, The Collections Framework and Connecting To Database

  • Files: Streams, byte streams, character stream
  • Text input/output, binary input/output
  • Random access file operations
  • File management using file class
  • The Collections Framework (java.util): Collections overview
  • Hierarchy of Collection Framework, Collection Interfaces
  • The Collection classes- Array List, Linked List, Hash Set, Tree Set, Priority Queue, Array Deque
  • Connecting to Database: Connecting to a database
  • Querying a database and processing the results
  • Updating data with JDBC

Discrete Mathematics and Graph Theory

105304
Theory Course • 6 Units
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Unit 1.0: Sets, Relation and Function

  • Operations and Laws of Sets
  • Cartesian Products
  • Binary Relation, Partial Ordering Relation, Equivalence Relation
  • Image of a Set
  • Sum and Product of Functions
  • Bijective functions, Inverse and Composite Function
  • Size of a Set, Finite and infinite Sets
  • Countable and uncountable Sets
  • Cantor's diagonal argument and The Power Set theorem
  • Schroeder-Bernstein theorem

Unit 2.0: Principles of Mathematical Induction

  • The Well-Ordering Principle
  • Recursive definition
  • The Division algorithm: Prime Numbers
  • The Greatest Common Divisor: Euclidean Algorithm
  • The Fundamental Theorem of Arithmetic
  • Basic counting techniques: inclusion and exclusion
  • Pigeon-hole principle
  • Permutation and combination

Unit 3.0: Propositional Logic

  • Syntax, Semantics
  • Validity and Satisfiability
  • Basic Connectives and Truth Tables
  • Logical Equivalence: The Laws of Logic
  • Logical Implication
  • Rules of Inference
  • The use of Quantifiers

Unit 4.0: Proof Techniques

  • Some Terminology
  • Proof Methods and Strategies
  • Forward Proof
  • Proof by Contradiction
  • Proof by Contraposition
  • Proof of Necessity and Sufficiency

Unit 5.0: Algebraic Structures and Morphism

  • Algebraic Structures with one Binary Operation
  • Semi Groups, Monoids, Groups
  • Congruence Relation and Quotient Structures
  • Free and Cyclic Monoids and Groups
  • Permutation Groups, Substructures, Normal Subgroups
  • Algebraic Structures with two Binary Operation
  • Rings, Integral Domain and Fields
  • Boolean Algebra and Boolean Ring
  • Identities of Boolean Algebra, Duality
  • Representation of Boolean Function
  • Disjunctive and Conjunctive Normal Form

Unit 6.0: Graphs and Trees

  • Graphs and their properties
  • Degree, Connectivity, Path, Cycle, Sub Graph, Isomorphism
  • Eulerian and Hamiltonian Walks
  • Graph Coloring
  • Coloring maps and Planar Graphs
  • Coloring Vertices, Coloring Edges, List Coloring
  • Perfect Graph, definition properties and Example
  • Rooted trees, trees and sorting
  • Weighted trees and prefix codes
  • Bi-connected component and Articulation Points
  • Shortest distances

Operating System

105305
Theory Course • 6 Units
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Unit 1.0: Introduction

  • Concept of Operating Systems
  • Generations of Operating systems
  • Types of Operating Systems
  • OS Services, System Calls
  • Structure of an OS: Layered, Monolithic, Microkernel
  • Concept of Virtual Machine
  • Case study on UNIX and WINDOWS Operating System

Unit 2.0: Processes

  • Definition, Process Relationship
  • Different states of a Process
  • Process State transitions
  • Process Control Block (PCB), Context switching
  • Thread: Definition, Various states
  • Benefits of threads, Types of threads
  • Concept of multithreads
  • Process Scheduling: Foundation and Scheduling objectives
  • Types of Schedulers
  • Scheduling criteria: CPU utilization, Throughput, Turnaround Time, Waiting Time, Response Time
  • Scheduling algorithms: Pre-emptive and Non pre-emptive, FCFS, SJF, RR
  • Multiprocessor scheduling
  • Real Time scheduling: RM and EDF

Unit 3.0: Inter-process Communication

  • Critical Section, Race Conditions
  • Mutual Exclusion
  • Hardware Solution, Strict Alternation, Peterson's Solution
  • The Producer - Consumer Problem
  • Semaphores, Event Counters, Monitors
  • Message Passing, Shared Memory
  • Classical IPC Problems: Reader's & Writer Problem, Dining Philosopher Problem etc.

Unit 4.0: Deadlocks

  • Definition
  • Necessary and sufficient conditions for Deadlock
  • Deadlock Prevention
  • Deadlock Avoidance: Banker's algorithm
  • Deadlock detection and Recovery

Unit 5.0: Memory Management

  • Basic concept, Logical and Physical address map
  • Memory allocation: Contiguous Memory allocation
  • Fixed and variable partition
  • Internal and External fragmentation and Compaction
  • Paging and Segmentation: Principle of operation
  • Page allocation, Hardware support for paging
  • Protection and sharing
  • Advantages and Disadvantages of paging and segmentation
  • Virtual Memory: Basics of Virtual Memory
  • Hardware and control structures
  • Locality of reference, Page fault, Working Set, Dirty page/Dirty bit
  • Demand paging
  • Page Replacement algorithms: Optimal, First in First Out (FIFO), Second Chance (SC), Not recently used (NRU) and Least Recently used (LRU)

Unit 6.0: File Management

  • Concept of File, Access methods, File types, File operation
  • Directory structure, File System structure
  • Allocation methods (contiguous, linked, indexed)
  • Free-space management (bit vector, linked list, grouping)
  • Directory implementation (linear list, hash table)
  • Efficiency and performance
  • Disk Management: Disk structure
  • Disk scheduling - FCFS, SSTF, SCAN, C-SCAN
  • Disk reliability, Disk formatting, Boot-block, Bad blocks
  • I/O Hardware: I/O devices, Device controllers, Direct memory access
  • Principles of I/O Software: Goals of Interrupt handlers
  • Device drivers, Device independent I/O software
  • Secondary-Storage Structure

Universal Human Values

105306
Theory Course • 6 Units
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Unit 1.0: Introduction to Value Education

  • Right Understanding, Relationship and Physical Facility (Holistic Development and the Role of Education)
  • Understanding Value Education Sharing about Oneself
  • Self-exploration as the Process for Value Education
  • Continuous Happiness and Prosperity – the Basic Human Aspirations
  • Exploring Human Consciousness
  • Happiness and Prosperity – Current Scenario
  • Method to Fulfil the Basic Human Aspirations

Unit 2.0: Harmony in the Human Being

  • Understanding Human being as the Co-existence of the Self and the Body
  • Distinguishing between the Needs of the Self and the Body
  • The Body as an Instrument of the Self
  • Understanding Harmony in the Self
  • Harmony of the Self with the Body
  • Programme to ensure self-regulation and Health

Unit 3.0: Harmony in the Family and Society

  • Harmony in the Family – the Basic Unit of Human Interaction
  • Trust – the Foundational Value in Relationship
  • Respect – as the Right Evaluation
  • Other Feelings
  • Justice in Human-to-Human Relationship
  • Understanding Harmony in the Society
  • Vision for the Universal Human Order

Unit 4.0: Harmony in the Nature/Existence

  • Understanding Harmony in the Nature
  • Interconnectedness, self-regulation and Mutual Fulfilment among the Four Orders of Nature
  • Realizing Existence as Co-existence at All Levels
  • The Holistic Perception of Harmony in Existence

Unit 5.0: Implications of the Holistic Understanding – a Look at Professional

  • Natural Acceptance of Human Values
  • Definitiveness of (Ethical) Human Conduct
  • A Basis for Humanistic Education
  • Humanistic Constitution and Universal Human Order
  • Competence in Professional Ethics
  • Holistic Technologies, Production Systems and Management Models-Typical Case Studies
  • Strategies for Transition towards Value-based Life and Profession

Unit 6.0: Professional Ethics and Applications

  • Competence in Professional Ethics
  • Holistic Technologies, Production Systems and Management Models-Typical Case Studies
  • Strategies for Transition towards Value-based Life and Profession

Indian Knowledge System

105307
Theory Course • 6 Units
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Unit 1.0: Introduction to Indian Knowledge Systems

  • Overview of IKS
  • Organization of IKS
  • Conception and constitution of knowledge in Indian tradition
  • The oral tradition
  • Models and Strategies of IKS

Unit 2.0: Overview of IKS Domains

  • The vedas as the basis of IKS
  • Overview of all the six vedangas

Unit 3.0: Relevance in Current Technical Education System I

  • Relevance of following IKS domains in present technical education system:
  • Arthashastra (Indian economics and political systems)
  • Ganita and Jyamiti (Indian mathematics, astronomy and geometry)
  • Rasayana (Indian chemical Sciences)

Unit 4.0: Relevance in Current Technical Education System II

  • Ayurveda (Indian Biological Sciences / Diet & Nutrition)
  • Jyotish Vidya (observational astronomy and calendar systems)
  • Prakriti Vidya (Indian system of terrestrial/ material sciences/ecology and atmospheric sciences)

Unit 5.0: Relevance in Current Technical Education System III

  • Vastu Vidya (Indian system of aesthetics-iconography and built-environment /architecture)
  • Nyaya Shastra (Indian systems of social ethics, logic and law)

Unit 6.0: Advanced IKS Domains

  • Shilpa and Natya Shastra (Indian classical arts: performing and fine arts)
  • Sankhya and Yoga Darshna (Indian psychology, yoga and consciousness studies)
  • Virkshayurveda (plant science/sustainable agriculture/food preservation methods)

Digital Electronics Lab

105301P
Laboratory Subject • 10 Units
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Topics Part 1

  • Universal Gates Identification and verification of NAND gate (IC #7400) and NOR gate (IC #7402) Construction and Verification of all other gate (AND, OR, NOT, XOR) USING a) Only NAND gate b) Only NOR gate
  • Identification and verification of NAND gate (IC #7400) and NOR gate (IC #7402)
  • Construction and Verification of all other gate (AND, OR, NOT, XOR) USING a) Only NAND gate b) Only NOR gate
  • Code Converter & Parity Generator and checker Identification & verification of NOT (7404), AND (7408) OR (7432) & XOR (7486) gates Design, construction and verification of 3-bit Binary to Gray convertor and 3-bit Grey to Binary convertor circuit Design, construction and verification of 3-bit odd/even Parity Generator and 4-bit odd/even parity checker circuit
  • Identification & verification of NOT (7404), AND (7408) OR (7432) & XOR (7486) gates
  • Design, construction and verification of 3-bit Binary to Gray convertor and 3-bit Grey to Binary convertor circuit
  • Design, construction and verification of 3-bit odd/even Parity Generator and 4-bit odd/even parity checker circuit
  • Adder, Subtractor & Magnitude comparator circuits Design, construction and verification of Half Adder and Half Subtractor circuit Design, construction and verification of Full Adder and Full Subtractor circuit Design, construction and verification of 1-bit and 4-bit Magnitude comparator BCD Adder/Subtractor
  • Design, construction and verification of Half Adder and Half Subtractor circuit
  • Design, construction and verification of Full Adder and Full Subtractor circuit
  • Design, construction and verification of 1-bit and 4-bit Magnitude comparator
  • BCD Adder/Subtractor
  • Decoder, MUX & DMUX Construction and verification of BCD to 7-segment decoder using IC # 7447 Verification of 4:1 MUX, 8:1 MUX & 16:1 MUX Verification of 1:4 DMUX, 1:8 DMUX Cascading of MUX and Cascading of Decoders
  • Construction and verification of BCD to 7-segment decoder using IC # 7447
  • Verification of 4:1 MUX, 8:1 MUX & 16:1 MUX
  • Verification of 1:4 DMUX, 1:8 DMUX
  • Cascading of MUX and Cascading of Decoders
  • Latches and Flip Flops Construction and Verification of a Latch circuit using NAND/NOR gates Construction and Verification of S-R Flip Flop using above Latch circuits Verification of J-K Flip Flop using IC # 7476 (Dual J-K FF) Construction and Verification of D-Flip Flop and T-Flip Flop using J-K FF (IC #7476) Construction and Verification of Master Slave J-K Flip Flop
  • Construction and Verification of a Latch circuit using NAND/NOR gates
  • Construction and Verification of S-R Flip Flop using above Latch circuits
  • Verification of J-K Flip Flop using IC # 7476 (Dual J-K FF)
  • Construction and Verification of D-Flip Flop and T-Flip Flop using J-K FF (IC #7476)
  • Construction and Verification of Master Slave J-K Flip Flop
  • Shift Registers Verification of D-FF using IC # 7474 (Dual D- FF) Construction and verification of a 2-bit Shift Right Register using IC # 7474 Construction and verification of a 2-bit Shift Left Register using IC # 7474 Verification of SISO, SIPO, PISO & PIPO Shift Registers
  • Verification of D-FF using IC # 7474 (Dual D- FF)
  • Construction and verification of a 2-bit Shift Right Register using IC # 7474
  • Construction and verification of a 2-bit Shift Left Register using IC # 7474
  • Verification of SISO, SIPO, PISO & PIPO Shift Registers
  • Synchronous & Asynchronous Counters Construction and verification of 2-bit Ripple counter using J-K FF Construction and verification of Mod-3 up and Mod-3 down synchronous counter Construction and verification of 2-bit Ring counter using J-K FF Construction and verification of 2-bit twisted Ring (Johnson) counter using J-K FF
  • Construction and verification of 2-bit Ripple counter using J-K FF
  • Construction and verification of Mod-3 up and Mod-3 down synchronous counter
  • Construction and verification of 2-bit Ring counter using J-K FF
  • Construction and verification of 2-bit twisted Ring (Johnson) counter using J-K FF
  • Design and construction of a 4 bit sequence generator
  • Digital to Analog Converter (DAC) Construction & Verification of D/A converters using: 1. Weighted Resistor type 2. R-2R ladder network type
  • Construction & Verification of D/A converters using: 1. Weighted Resistor type 2. R-2R ladder network type
  • Analog to Digital Converter (ADC) Construction & Verification of A/D Converter using: 1. Counter type 2. Successive Approximation type
  • Construction & Verification of A/D Converter using: 1. Counter type 2. Successive Approximation type
  • Familiarization with multisim. Design of various Digital Circuits using Multisim.

Topics Part 2

  • Identification and verification of NAND gate (IC #7400) and NOR gate (IC #7402)
  • Construction and Verification of all other gate (AND, OR, NOT, XOR) USING a) Only NAND gate b) Only NOR gate

Topics Part 3

  • Identification & verification of NOT (7404), AND (7408) OR (7432) & XOR (7486) gates
  • Design, construction and verification of 3-bit Binary to Gray convertor and 3-bit Grey to Binary convertor circuit
  • Design, construction and verification of 3-bit odd/even Parity Generator and 4-bit odd/even parity checker circuit

Topics Part 4

  • Design, construction and verification of Half Adder and Half Subtractor circuit
  • Design, construction and verification of Full Adder and Full Subtractor circuit
  • Design, construction and verification of 1-bit and 4-bit Magnitude comparator
  • BCD Adder/Subtractor

Topics Part 5

  • Construction and verification of BCD to 7-segment decoder using IC # 7447
  • Verification of 4:1 MUX, 8:1 MUX & 16:1 MUX
  • Verification of 1:4 DMUX, 1:8 DMUX
  • Cascading of MUX and Cascading of Decoders

Topics Part 6

  • Construction and Verification of a Latch circuit using NAND/NOR gates
  • Construction and Verification of S-R Flip Flop using above Latch circuits
  • Verification of J-K Flip Flop using IC # 7476 (Dual J-K FF)
  • Construction and Verification of D-Flip Flop and T-Flip Flop using J-K FF (IC #7476)
  • Construction and Verification of Master Slave J-K Flip Flop

Topics Part 7

  • Verification of D-FF using IC # 7474 (Dual D- FF)
  • Construction and verification of a 2-bit Shift Right Register using IC # 7474
  • Construction and verification of a 2-bit Shift Left Register using IC # 7474
  • Verification of SISO, SIPO, PISO & PIPO Shift Registers

Topics Part 8

  • Construction and verification of 2-bit Ripple counter using J-K FF
  • Construction and verification of Mod-3 up and Mod-3 down synchronous counter
  • Construction and verification of 2-bit Ring counter using J-K FF
  • Construction and verification of 2-bit twisted Ring (Johnson) counter using J-K FF

Topics Part 9

  • Construction & Verification of D/A converters using: 1. Weighted Resistor type 2. R-2R ladder network type

Topics Part 10

  • Construction & Verification of A/D Converter using: 1. Counter type 2. Successive Approximation type

Prescribed Experiments

  1. Universal Gates Identification and verification of NAND gate (IC #7400) and NOR gate (IC #7402) Construction and Verification of all other gate (AND, OR, NOT, XOR) USING a) Only NAND gate b) Only NOR gate
  2. Identification and verification of NAND gate (IC #7400) and NOR gate (IC #7402)
  3. Construction and Verification of all other gate (AND, OR, NOT, XOR) USING a) Only NAND gate b) Only NOR gate
  4. Code Converter & Parity Generator and checker Identification & verification of NOT (7404), AND (7408) OR (7432) & XOR (7486) gates Design, construction and verification of 3-bit Binary to Gray convertor and 3-bit Grey to Binary convertor circuit Design, construction and verification of 3-bit odd/even Parity Generator and 4-bit odd/even parity checker circuit
  5. Identification & verification of NOT (7404), AND (7408) OR (7432) & XOR (7486) gates
  6. Design, construction and verification of 3-bit Binary to Gray convertor and 3-bit Grey to Binary convertor circuit
  7. Design, construction and verification of 3-bit odd/even Parity Generator and 4-bit odd/even parity checker circuit
  8. Adder, Subtractor & Magnitude comparator circuits Design, construction and verification of Half Adder and Half Subtractor circuit Design, construction and verification of Full Adder and Full Subtractor circuit Design, construction and verification of 1-bit and 4-bit Magnitude comparator BCD Adder/Subtractor
  9. Design, construction and verification of Half Adder and Half Subtractor circuit
  10. Design, construction and verification of Full Adder and Full Subtractor circuit
  11. Design, construction and verification of 1-bit and 4-bit Magnitude comparator
  12. BCD Adder/Subtractor
  13. Decoder, MUX & DMUX Construction and verification of BCD to 7-segment decoder using IC # 7447 Verification of 4:1 MUX, 8:1 MUX & 16:1 MUX Verification of 1:4 DMUX, 1:8 DMUX Cascading of MUX and Cascading of Decoders
  14. Construction and verification of BCD to 7-segment decoder using IC # 7447
  15. Verification of 4:1 MUX, 8:1 MUX & 16:1 MUX
  16. Verification of 1:4 DMUX, 1:8 DMUX
  17. Cascading of MUX and Cascading of Decoders
  18. Latches and Flip Flops Construction and Verification of a Latch circuit using NAND/NOR gates Construction and Verification of S-R Flip Flop using above Latch circuits Verification of J-K Flip Flop using IC # 7476 (Dual J-K FF) Construction and Verification of D-Flip Flop and T-Flip Flop using J-K FF (IC #7476) Construction and Verification of Master Slave J-K Flip Flop
  19. Construction and Verification of a Latch circuit using NAND/NOR gates
  20. Construction and Verification of S-R Flip Flop using above Latch circuits
  21. Verification of J-K Flip Flop using IC # 7476 (Dual J-K FF)
  22. Construction and Verification of D-Flip Flop and T-Flip Flop using J-K FF (IC #7476)
  23. Construction and Verification of Master Slave J-K Flip Flop
  24. Shift Registers Verification of D-FF using IC # 7474 (Dual D- FF) Construction and verification of a 2-bit Shift Right Register using IC # 7474 Construction and verification of a 2-bit Shift Left Register using IC # 7474 Verification of SISO, SIPO, PISO & PIPO Shift Registers
  25. Verification of D-FF using IC # 7474 (Dual D- FF)
  26. Construction and verification of a 2-bit Shift Right Register using IC # 7474
  27. Construction and verification of a 2-bit Shift Left Register using IC # 7474
  28. Verification of SISO, SIPO, PISO & PIPO Shift Registers
  29. Synchronous & Asynchronous Counters Construction and verification of 2-bit Ripple counter using J-K FF Construction and verification of Mod-3 up and Mod-3 down synchronous counter Construction and verification of 2-bit Ring counter using J-K FF Construction and verification of 2-bit twisted Ring (Johnson) counter using J-K FF
  30. Construction and verification of 2-bit Ripple counter using J-K FF
  31. Construction and verification of Mod-3 up and Mod-3 down synchronous counter
  32. Construction and verification of 2-bit Ring counter using J-K FF
  33. Construction and verification of 2-bit twisted Ring (Johnson) counter using J-K FF
  34. Design and construction of a 4 bit sequence generator
  35. Digital to Analog Converter (DAC) Construction & Verification of D/A converters using: 1. Weighted Resistor type 2. R-2R ladder network type
  36. Construction & Verification of D/A converters using: 1. Weighted Resistor type 2. R-2R ladder network type
  37. Analog to Digital Converter (ADC) Construction & Verification of A/D Converter using: 1. Counter type 2. Successive Approximation type
  38. Construction & Verification of A/D Converter using: 1. Counter type 2. Successive Approximation type
  39. Familiarization with multisim. Design of various Digital Circuits using Multisim.

Data Structure and Algorithms Lab

105302P
Laboratory Subject • 1 Units
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Topics Part 1

  • Write a program to read a linear list of items and store it in an array.
  • Write a program to implement binary search.
  • Write a program to implement stack using array.
  • Write a program to implement stack using linked list.
  • Write a program to convert infix expression into postfix expression.
  • Write a program to implement queue using array.
  • Write a program to insert element in a circular queue using array.
  • Write a program to implement queue using Linked List.
  • Implement single linked list: 1. Create a single linked list 2. Count number of nodes 3. Traverse the linked list
  • Insert node in singly linked list: 1. from beginning 2. at certain position
  • Delete a node of singly linked list: 1. from beginning 2. from end 3. at certain position 4. delete entire list 5. Reverse the single linked list
  • Insert a node in the doubly linked list: 1. from beginning 2. from end 3. at a certain position 4. Reverse the list
  • Delete a node of doubly linked list: 1. from beginning 2. from end 3. at certain position
  • Create a node of circular singly linked list and circular doubly linked list.
  • Write a program for tree traversal: 1. Preorder 2. Inorder 3. Postorder

Prescribed Experiments

  1. Write a program to read a linear list of items and store it in an array.
  2. Write a program to implement binary search.
  3. Write a program to implement stack using array.
  4. Write a program to implement stack using linked list.
  5. Write a program to convert infix expression into postfix expression.
  6. Write a program to implement queue using array.
  7. Write a program to insert element in a circular queue using array.
  8. Write a program to implement queue using Linked List.
  9. Implement single linked list: 1. Create a single linked list 2. Count number of nodes 3. Traverse the linked list
  10. Insert node in singly linked list: 1. from beginning 2. at certain position
  11. Delete a node of singly linked list: 1. from beginning 2. from end 3. at certain position 4. delete entire list 5. Reverse the single linked list
  12. Insert a node in the doubly linked list: 1. from beginning 2. from end 3. at a certain position 4. Reverse the list
  13. Delete a node of doubly linked list: 1. from beginning 2. from end 3. at certain position
  14. Create a node of circular singly linked list and circular doubly linked list.
  15. Write a program for tree traversal: 1. Preorder 2. Inorder 3. Postorder

Object Oriented Programming Using JAVA Lab

105303P
Laboratory Subject • 1 Units
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Topics Part 1

  • Program to Demonstrate Basic Java Syntax and Control Structures
  • Program Using Classes, Objects, Methods, and Constructors
  • Program on Method Overloading and Constructor Overloading
  • Program to Demonstrate Inheritance and Use of 'super' Keyword
  • Program Using Method Overriding and Runtime Polymorphism
  • Program to Implement Abstract Class and Interface
  • Program on User-Defined Exceptions
  • Multithreading Program with Synchronization
  • File Handling Program Using Byte Stream & Character Stream
  • Program Using Java Collections Framework & JDBC Connectivity

Prescribed Experiments

  1. Program to Demonstrate Basic Java Syntax and Control Structures
  2. Program Using Classes, Objects, Methods, and Constructors
  3. Program on Method Overloading and Constructor Overloading
  4. Program to Demonstrate Inheritance and Use of 'super' Keyword
  5. Program Using Method Overriding and Runtime Polymorphism
  6. Program to Implement Abstract Class and Interface
  7. Program on User-Defined Exceptions
  8. Multithreading Program with Synchronization
  9. File Handling Program Using Byte Stream & Character Stream
  10. Program Using Java Collections Framework & JDBC Connectivity

Operating System Lab

105305P
Laboratory Subject • 1 Units
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Topics Part 1

  • Write a program to implement FCFS scheduling algorithm.
  • Write a program to implement SJF scheduling algorithm.
  • Write a program to implement priority scheduling algorithm.
  • Write a program to implement round robin scheduling.
  • Write a program to implement banker's algorithm.
  • Write a device driver for any device or peripheral.
  • Write a program to implement disk scheduling algorithm.
  • Write a program to implement dining philosopher problem.
  • Write a program to implement producer consumer problem.
  • Write a program to implement LRU page replacement algorithm.

Prescribed Experiments

  1. Write a program to implement FCFS scheduling algorithm.
  2. Write a program to implement SJF scheduling algorithm.
  3. Write a program to implement priority scheduling algorithm.
  4. Write a program to implement round robin scheduling.
  5. Write a program to implement banker's algorithm.
  6. Write a device driver for any device or peripheral.
  7. Write a program to implement disk scheduling algorithm.
  8. Write a program to implement dining philosopher problem.
  9. Write a program to implement producer consumer problem.
  10. Write a program to implement LRU page replacement algorithm.

Internship – I

105308
Laboratory Subject • Course Details
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